A. Technical Field
The present invention relates to the field of electronics and data communications, and more particularly, to a programmable frequency synthesizer that generates both in-phase and quadrature-phase clock signals over a wide bandwidth.
B. Background of the Invention
Frequency synthesizers are electronic components for generating specific frequencies in reference to a fixed frequency provided by an external reference oscillator, and they are widely applied in modern communication systems, including radio receivers, mobile telephones, GPS systems and satellite receivers. The reference oscillator is normally a crystal oscillator that includes a vibrating crystal of piezoelectric material, so the reference frequency is maintained precise and stable. The core of a frequency synthesizer typically comprises a phase-locked loop (PLL) that aligns the phase and frequency of the output signal with the input reference. To obtain a fractional division ratio, a prescaler is used to reduce the input reference frequency by an integer ratio before it is sent to the phase-locked loop.
At a low reference frequency, the performance and cost efficiency tends to be degraded for the phase-locked loop. A typical phase-locked loop comprises a phase detector (PD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a feedback frequency divider. The phase detector detects the phase difference between the output of the feedback frequency divider and the reference input; and the charge pump converts this phase difference to current. However, at a low operating frequency, the small charge-pump current increases the implementation difficulty. Moreover, the subsequent loop filter requires the use of large capacitors to reach a narrow bandwidth, typically less than one tenth of the input reference frequency. Regardless of this loop filter being on- or off-chip, cost efficiency of the entire component may be significantly reduced due to the large chip area or additional on-board components. In addition, with a low cutoff frequency, the frequency synthesizer requires a long time to settle; for example, for a loop bandwidth of 5 kHz, the settling time may last 200 μsec. Therefore, frequency synthesizers functioning at low frequencies are undesirable due to performance and cost efficiency degradation of the phase-locked loop.
Most communication systems only require their internal clock signals to be programmed to a number of frequencies within a limited range. However, for data transmission applications such as the Mobile Industry Processor Interface (MIPI), the clocking frequencies must vary over a wide range from fractions to multiples of the reference frequency while both in-phase and quadrature-phase (I/Q) clock signals are required. Due to the aforementioned limitations of the phase-locked loop, the conventional frequency synthesizer needs to be modified to accommodate low reference frequencies. One solution is the digital Σ-Δ fractional PLL. In the Σ-Δ PLL, the feedback frequency divider is usually a dual-modulus divider with the modulus control being the output of a digital Σ-Δ modulator. This approach not only increases design complexity but also introduces undesirable jitter and spurious sidebands. A need exists to provide a convenient solution to generate programmable clock signals covering a wide bandwidth.
A quadrature-phase clock signal is a signal delayed from the clock a quarter of cycle. A typical method of generating the quadrature-phase signal is to double the input clock, and then followed by a divide-by-two counter. Conventionally, frequency doubling is implementable using XOR logic gates or inside the VCO. However, doubling the frequency increases design complexity, power consumption, and may inject high-frequency glitches to the output signals. A need exists to output clock signals while avoiding frequency doubling without increasing the design complexity or power consumption.
Programmability and I/Q outputs present challenges for clock generation, especially for high-performance, low-cost and easy-to-implement solutions.